1. Field of the Invention
The present invention relates to a spin-transfer torque magnetic random access memory (STTMRAM) cell, and, more particularly, to a configuration of STTMRAM cells having significantly smaller cell size and a tolerance for higher switching current density.
2. Description of the Prior Art
It is anticipated that spin transfer torque magnetic random access memory (STTMRAM) will be commonly employed as non-volatile memory in a wide variety of applications in the near future. Benefits realized by this type of memory include smaller memory size, scalability of manufacturing, and low current consumption, among others.
At the most abstract level, STTRAM comprises a plurality of STTRAM memory cells, otherwise known a memory array. Each memory cell includes a memory element and an access (or select) transistor. Generally, each memory element includes a magnetic tunnel junction (MTJ) having a free layer, fixed layer, and a barrier layer there between; as well as any other layers necessary or advantageous to the operation of the MTJ (e.g., a cap layer, pinning layer, or under layer).
An MTJ may typically be switched between a parallel or anti-parallel state. In the parallel state, the storage layer, commonly referred to as the free layer of the MTJ, has a magnetic orientation that is substantially in the same direction as that of the MTJ's fixed layer. The magnetic orientation of the fixed layer is static, being permanently fixed during fabrication, while the magnetic orientation of the free layer is intentionally capable of switching from one direction to an opposite direction so as to differentiate between two binary states, i.e. ‘0’ or ‘1’. In an anti-parallel state, the magnetic orientation of the free layer is opposite to the magnetic orientation the fixed layer. The resistance of the MTJ changes depending on its state of parallel and anti-parallel. Typically, the resistance of the MTJ is higher at an anti-parallel state than at a parallel state.
A memory cell typically includes a MTJ and an access transistor. The latter being used to read and write to the MTJ, basically allowing access thereto. However, the requirement of having one transistor per MTJ makes for a large memory cell. Moreover, the access transistor need be large enough to accommodate the large current required for causing the MTJ to switch from one magnetic orientation to another. Currently, for an given switching current of an MTJ, the memory cell size is intolerably large, in the order of greater than 20F2, where F represents Minimum Feature Size.
The process of reading prior art STTRAM memory cells, i.e., a “read operation”, is not sufficiently reliable and requires improvement. An example of where improvement is necessary includes reducing the sense current, the current applied to the MTJ during a read operation, to be significantly lower than the current which is used to perform a write operation (write current). Otherwise the state (or magnetization direction) of the MTJ may be undesirably changed (e.g., written) during what is intended to be a read operation. This is unacceptable because the state of the MTJ is representative of the bit value stored, and, if erroneously changed, the data thereby is corrupted.
The number of devices is increasing in which STTRAM is a viable storage option. However, as the applications for these devices become ever more demanding of the hardware, the actual devices are shrinking in response to consumer demands for portability. Thus, as memory capacities increase, the footprint of the memory component must concurrently decrease.
Therefore, in light of the foregoing, what is needed is a shared transistor STTMRAM memory cell made of a memory element and an access transistor, the shared transistor configuration reducing the memory cell footprint while increasing both the memory element density and the switching current density.